Po-Hui Yang, Professor

楊博惠 教授

  • 職稱/ 教授
  • 電話/(05)5524654,(05)5342601#4340
  • 傳真/(05)5312063
  • E-mail/phyang@yuntech.edu.tw
  • 研究室/ES501
  • 實驗室/感知系統積體電路與訊號處理實驗室 ES915 (#4395)
  • 學歷/國立中正大學 - 電機工程研究所 博士
  • 專長/高速數位時脈系統IC、低功率嵌入式巨集IC、系統級IC封裝

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學士:1993年、國立台灣海洋大學海洋航海技術系、航電組、工學士學位。 
碩士:1995年、國立台灣師範大學工業教育所、工業教育碩士學位。
博士:2001年、國立中正大學電機工程研究所、工程博士學位。
2001年至2003年、南台科技大學電子系助理教授。
2003年至2004年、工業技術研究院(工研院)SoC技術中心(STC)高性能數位IC設計工程師 及 電路設計部課長。
2004年迄今、國立雲林科技大學電子工程系,助理教授,副教授,教授。

一、學術期刊論文

  1. Po-Hui Yang*, Che-Tsung Chan, and Ying-Sheng Chang, “A Potentiometric Uric Acid Biosensor Integrated with Temperature Correction Readout Circuit on Flexible PCB,” IEEE Sensors Journal, Vol. 23, No. 9, pp. 9086-9092, May 2023. (SCIE)
  2. Po-Hui Yang*, Che-Tsung Chan, and Ying-Sheng Chang,” ZnO Film Flexible Printed Circuit Board pH Sensor Measurement and Characterization,” IEEE Access, Vol. 10, pp. 96091-96099, Sep. 2022. (SCIE)
  3. Po-Hui Yang*, Che-Tsung Chan, and Ying-Sheng Chang, “A Flexible Printed Circuit Board-Based ZnO Enzymatic Uric Acid Potentiometric Biosensor Measurement and Characterization,” IEEE Journal of the Electron Devices Society, Vol. 11, pp. 114 - 121, Feb. 2023. (SCIE)
  4. Po-Hui Yang*, Ying-Sheng Chang, and Che-Tsung Chan, “Aluminum-Doped Zinc Oxide Enzymatic Dopamine Biosensor Integrated With Potentiometric Readout Circuit Board,” IEEE Sensors Journal, Vol. 23, No. 3, pp. 1809 - 1817, Jan. 2023. (SCIE)
  5. Po-Hui Yang*, Ying-Sheng Chang, and Che-Tsung Chan, “A Potentiometric Enzymatic Flexible Dopamine Biosensor With Temperature Compensation Based on the Flexible Printed Circuit Board,” IEEE Transactions on Instrumentation and Measurement, Vol. 72, 8 pages, July 2023. (SCIE)
  6. Po-Hui Yang*, Ying-Sheng Chang, and Che-Tsung Chan, “ZnO and AZO Film Potentiometric pH Sensors Based on Flexible Printed Circuit Board,” Chemosensors, vol. 10, no. 8, 14 pages, July 2022. (SCIE)
  7. Jung-Chuan Chou, Kun-Tse Lee, Po-Hui Yang, Po-Yu Kuo, Yu-Hsun Nien, and Chih-Hsien Lai, “Non-Enzymatic Ascorbic Acid Sensor Simultaneous Applied to Potentiometric and Amperometric Measurement,” IEEE Transactions on Nanotechnology, vol. 21, pp. 674-684, Nov. 2022. (SCIE)
  8. Jung-Chuan Chou, Kun-Tse Lee, Po-Hui Yang, Po-Yu Kuo, Yu-Hsun Nien, Chih-Hsien Lai, and Ying-Sheng Chang, “ Potentiometric Nonenzymatic Ascorbic Acid Sensor for Static and Dynamic Measurements,” IEEE Transactions on Instrumentation and Measurement, vol. 72, 10 pages, Jan. 2023. (SCIE)
  9. Yu-Hsun Nien, Zhi-Xuan Kang, Jung-Chuan Chou, Po-Hui Yang, Po-Yu Kuo, Chih-Hsien Lai, Zhe-Xin Dong, Yung-Yu Chen, Yi-Ting Wu, Kun-Tse Lee, and Tai-Hui Wang, “Application of Non-Enzymatic Lactate Sensor Modified by Graphitic Carbon Nitride/Iron-Platinum Nanoparticles and Combined With the Low Power Consumption Instrumentation Amplifier and Calibration Readout Circuit,” IEEE Transactions on Instrumentation and Measurement, vol. 72, 8 pages, Mar. 2023. (SCIE)
  10. Jung-Chuan Chou, Ruei-Hong Syu, Chih-Hsien Lai, Po-Yu Kuo, Po-Hui Yang, Yu-Hsun Nien, Yu-Che Lin, Zhen-Rong Yong, and Yi-Ting Wu, "Optimization and Application of TiO2 Hollow Microsphere Modified Scattering Layer for the Photovoltaic Conversion Efficiency of Dye-Sensitized Solar Cell," IEEE Transactions on Semiconductor Manufacturing, vol. 35, pp. 363-371, May 2022. (SCIE)
  11. Jung-Chuan Chou, Ruei-Hong Syu, Po-Hui Yang, Po-Yu Kuo, Yu-Hsun Nien, Chih-Hsien Lai, Po-Feng Chen, Yi-Ting Wu, and Shang-Wen Zhuang, " Increasing the Photovoltaic Performance of Dye-Sensitized Solar Cells by Zinc Oxide Film as a Recombination Blocking Layer," IEEE Transactions on Electron Devices, vol. 69, pp. 5004-5011, Sep. 2022. (SCIE)
  12. Jung-Chuan Chou, Jun-Xiang Chang, Po-Hui Yang, Chih-Hsien Lai, Po-Yu Kuo, Yu-Hsun Nien, Ruei-Hong Syu, and Po-Feng Cheng, " The Application of Dye-Sensitized Solar Cell Using rGO and MBs in Series-Parallel Under Low Illumination," IEEE Access, vol. 10, pp. 90467 - 90473, Aug. 2022. (SCIE)
  13. Yu-Hsun Nien, Yi-Ting Wu, Jung-Chuan Chou, Po-Hui Yang, Chih-Sung Ho, Chih-Hsien Lai, Po-Yu Kuo, Ruei-Hong Syu, Shang-Wen Zhuang, and Po-Feng Chen, "Photovoltaic Performance of Dye-Sensitized Solar Cells Under Low Illumination by Modification of a Photoanode With ZnFe2O4/TiO2 Nanofibers," IEEE Transactions on Nanotechnology, vol. 21, pp. 606-612, Oct. 2022. (SCIE)
  14. Jung-Chuan Chou, Jun-Xiang Chang, Po-Hui Yang, Ruei-Hong Syu, Chih-Hsien Lai, Po-Yu Kuo, Yu-Hsun Nien, Yu-Che Lin, Po-Feng Chen, and Shang-Wen Zhuang, “Photovoltaic Properties of the Titanium Dioxide Compact Layer and Reduced Graphene Oxide for Dye-Sensitized Solar Cells Under Different Light Intensities,” IEEE Journal of Photovoltaics, vol. 13, pp. 87-94, Dec. 2022. (SCIE)
  15. Jung-Chuan Chou, Ruei-Hong Syu, Po-Hui Yang, Po-Yu Kuo, Yu-Hsun Nien, Chih-Hsien Lai, Po-Feng Chen, Yi-Ting Wu, and Shang-Wen Zhuang, “Graphene Quantum Dots as a Co-Sensitizer With Improving Light Absorption for Dye-Sensitized Solar Cells,” IEEE Transactions on Nanotechnology, vol. 22, pp. 20-27, Jan. 2023. (SCIE)
  16. Yu-Hsun Nien, Shang-Wen Zhuang, Jung-Chuan Chou, Po-Hui Yang, Chih-Hsien Lai, Po-Yu Kuo, Chih-Sung Ho, Yi-Ting Wu, Ruei-Hong Syu, and Po-Feng Chen, “Photovoltaic Measurement Under Different Illumination of the Dye-Sensitized Solar Cell With the Photoanode Modified by Fe2O3/g-C3N4/TiO2 Heterogeneous Nanofibers Prepared by Electrospinning With Dual Jets,” IEEE Transactions on Semiconductor Manufacturing, vol. 36, pp. 291-297, May 2023. (SCIE)
  17. Jung-Chuan Chou, Po-Feng Chen, Po-Hui Yang, Chih-Hsien Lai, Po-Yu Kuo, Yu-Hsun Nien, Ruei-Hong Syu, Yi-Ting Wu, and Shang-Wen Zhuang, “Modifications to the Scattering Layer of a Dye-Sensitized Solar Cell Photoanode With Bifunctional WO3 Hollow Spheres for Increased Electron Transfer and Scattering Effect,” IEEE Transactions on Electron Devices, vol. 70, pp. 2415-2423, May 2023. (SCIE)
  18. Yu-Hsun Nien, Yi-Ting Wu, Jung-Chuan Chou, Po-Hui Yang, Chih-Sung Ho, Chih-Hsien Lai, Po-Yu Kuo, Ruei-Hong Syu, Shang-Wen Zhuang, and Po-Feng Chen, “Photovoltaic Performance of Dye-Sensitized Solar Cell by Modification of Photoanode With PbTiO3–ZnFe2O4/TiO2 Nanofibers,” IEEE Transactions on Electron Devices, vol. 70, pp. 3780-3787, Jul. 2023. (SCIE)
  19. Po-Hui Yang, 2011, Cost-effective Variable Node Using Thermalcode Addition for LDPC Decoders, IEICE Electronics Express, Vol.8, pp.1948-1953. (SCI)
  20. Po-Hui Yang, 2009, A Concise Min-Sum LDPC Decoder Using Simplified Comparators, International Journal of Electrical Engineering, Vol.16, No.6, pp.473-478. (EI)(97-2220-E-224-001)
  21. Po-Hui Yang, 2009, A Low-Complexity and High-Performance 2D Look-up Table for LDPC Hardware Implementation, IEICE Fundamentals, Vol.92-A, No.11, pp.2941-2944. (SCI)(96-2221-E-224-079)
  22. Po-Hui Yang and J. S. Wang, 2002, Design of Low-Voltage CMOS Pulsewidth Control Loops for SoC Applications. (SCI)
  23. Jinn-Shyan Wang, Shang-Jyh Shieh, Jei-Chien Wang and Po-Hui Yang, 2001, The design of a standard cell library for low-power / low-voltage VLSI applications. (SCI)
  24. Jinn-Shyan Wang and Po-Hui Yang, 2001, A Low-Voltage CMOS Pulsewidth Control Loop Using a Push-Pull Charge Pump. (SCI)
  25. Jinn-Shyan Wang, Po-Hui Yang and Duo Sheng, 2000, Design of a 3-V 300-MHz low-power 8 x 8-bit pipelined multiplier using pulse-triggered TSPC flip-flops. (SCI)

二、學術會議論文

  1. Jyun-Da Huang, Jhih-Yu Syu, and Po-Hui Yang, 2019, A Voltage Compensation Embedded All Digital Temperature Sensors, The 30th VLSI Design/CAD Symposium, 2019/08/06-09, 中正大學, 高雄, pp.26-28.
  2. Liao Hung-Jen, Zhu Ji-Gang, Cheng Bo-Han, Yang Po-Hui, 2019, A Dead-zone Reduction Phase Detector Circuit Design for Digital Delay Lock Loops, The 14th Intelligent Living Technology Conference (ILT2019), 2019/06/14, 勤益科技大學, 台中市,勤益科技大學, pp.355-362.
  3. Syu Jhih-Yu, Huang Jyun-Da, Yang Po-Hui, 2019, A Sensitivity Adjustable Embedded All Digital Temperature Sensor, 2019 Conference on Information Technology and Applications in Outlying Islands (ITAOI2019), 2019/05/24-25, 中興大學, 台中市,中興大學, pp.833-836.
  4. 楊博惠, 2018, 非路徑選擇寬頻快速鎖定全數位延遲鎖相迴路, The 13th Intelligent Living Technology Conference (ILT2018), 2018/06/01, 勤益科技大學, 台中市,勤益科技大學, pp.icd8-icd11.
  5. 楊博惠, 2018, 次皮秒級850MHz-4.5GHz寬頻快速鎖定全數位延遲鎖相迴路, The 13th Intelligent Living Technology Conference (ILT2018), 2018/06/01, 勤益科技大學, 台中市,勤益科技大學, pp.icd1-icd3.
  6. 楊博惠, 2018, 被動式100W高功率T型偏壓器研製及實體可見光通訊平台建置, 2018第十七屆離島資訊技術與應用研討會, 2018/05/25-27, 澎湖科技大學, 澎湖,澎湖科技大學, pp.107-110.
  7. 楊博惠, 2018, 應用於IC構裝非破壞性故障檢測之高頻阻抗響應特徵分析技術, 2018第十七屆離島資訊技術與應用研討會, 2018/05/25-27, 澎湖科技大學, 澎湖,澎湖科技大學, pp.100-103.
  8. 楊博惠, 黃靖珽, 王萱鍢, 2017, Wide Measurement Range High-Resolution Single-Path Variable Time Vernier Delay Line Circuits, 2017 Cross Strait Quad-Regional Radio Wireless Conference, 2017/07/21-24, 華南理工大學, 湖南, pp.101-103.
  9. Po-Hui Yang, Jing-Min Chen, Ching-Ken Chen, 2015, A Temperature Sensor Cell Design with System in Pakage Application, The 4th International Conference on Frontier Computing (FC 2015), 2015/09/09-11, IET, Bangkok, pp.626-631.
  10. Po-Hui Yang, Jing-Min Chen, Zi-Min Hong, 2015, All-digital High-Speed Wide-Range Binary Detecting Pulse-Width Lock Loops, The 4th International Conference on Frontier Computing (FC 2015), 2015/09/09-11, IET, Bangkok, pp.619-625.
  11. Po-Hui Yang, Jing-Min Chen, Po-Yu Kuo, Chia-Chun Wu, 2015, Application on Metastable Measurementwith Wide Range High Resolution VDL Circuit, WASET, International Conference on Electrical Engineering and Technology 2015., 2015/05/28-29, World Academy of Science, Engineering and Technology, Tokyo, pp.3233-3236.
  12. 楊博惠, 2012, A Light input Loading High-Speed Differential D Flip-Flop, The 2nd Conference on Applications of Innovation & Invention, 2012/11/23-24, 勤益科大, 台中市,勤益科大.
  13. 楊博惠, 2012, A Wide Range and High Resolution Vernier Delay Line for Metastability Measurement Applications, The 2nd Conference on Applications of Innovation & Invention, 2012/11/23-24, 勤益科大, 台中市、勤益科大.
  14. 楊博惠, 2012, A High-Performance 128-to-1 CMOS Multiplexer Tree, 2012 Intelligent Signal Processing and Communication Systems, 2012/11/05-07, IEEE, 新北市,淡江大學.
  15. 楊博惠, 2012, The Analysis and Improvement of Metastability in Basic Feedback-connected Logic Circuit, The 7th Intelligent Living Technology Conference, 2012/06/01-02, 勤益科大, 台中市,勤益科大.
  16. 楊博惠, 2012, A High-Speed CMOS Many-to-One Multiplexer Design, The 7th Intelligent Living Technology Conference, 2012/06/01-02, 勤益科大, 台中市,勤益科大.
  17. 楊博惠, 2012, Embedded Ring Oscillator Based Low Error Temperature Sensor Design, The 7th Intelligent Living Technology Conference, 2012/06/01-02, 勤益科大, 台中市,勤益科大.
  18. 楊博惠, 2012, A Fast Wake-up Power Gating Technique with Inducing A Balanced Rush Current, 2012 International Symposium on Circuits and Systems, 2012/05/20-23, IEEE, 首爾.
  19. 楊博惠, 2011, A Voltage Fluctuation Immunity Standard Cell Based Temperature Sensor, The 1st Conference on Applications of Innovation & Invention, 2011/11/24-25, 勤益科大, 台中市,勤益科大, pp.274-278.
  20. 楊博惠, 2011, A Fast Single Delay Line Pulsewidth Lock Loops, The 1st Conference on Applications of Innovation & Invention, 2011/11/24-25, 勤益科大, 台中市,勤益科大, pp.310-313.
  21. 楊博惠, 2011, The Analysis and Improvement of Metastability in Basic Feedback-connected Logic Circuits, The 1st Conference on Applications of Innovation & Invention, 2011/11/24-25, 勤益科大, 台中市,勤益科大, pp.314-318.
  22. Cheng-Chung Liao, Chao-Ching Tang and Po-Hui Yang, 2010, An Analysis of Metastability in High-Speed D-Flip Flops, 2010 International Conference on High-Speed Circuits Design (HSCD' 10), 2010/10/28-29, 勤益科大, 台中市,勤益科大, pp.75-80.
  23. Yao-Sian Su, Ming-Xian Liu and Po-Hui Yang, 2010, A Parallel Connection Embedded All Digital Temperature Sensing System Design, International Conference on High-Speed Circuits Design (HSCD'10), 2010/10/28-29, 勤益科大電子系, 台中市,勤益科大, pp.69-74. (98-2221-E-224-053-)
  24. 魏劭全, 楊博惠, 2010, A Parallel CORDIC Using Array Double Update Technique for QR Decomposition Hardware Implementation, 2010 Conference on Innovative Applications of System Prototyping and Circuits Design, 2010/10/15, 清雲科技大學, 桃園縣,清雲科大, pp.182-186.
  25. 吳星儀, 連振凱, 楊博惠, 2010, Prototyping Design for Lower PAPR Computational Complexity for OFDM System, 2010 Conference on Innovative Applications of System Prototyping and Circuits Design, 2010/10/15, 清雲科技大學, 桃園縣,清雲科大, pp.138-142.
  26. Jia-Ping Liu, Sing-Yi Wu, and Po-Hui Yang, 2010, A Low Cost Variable Node Using Thermalcode Addition for LDPC Decoder, 2010 VLSI Design/CAD Symposium, 2010/08/03-06, 成功大學, 高雄, pp.655-658.
  27. Ming-Jen Chen, Yi-Mao Hsiao, Yuan-Sun Chu and Po-Hui Yang, 2010, Documents Relationship Creation with Vocabulary Probability Analysis, 2010 International Conference on Information and Communication Technologies, 2010/05/25-29, World Academy of Science, Engineering and Technology, Tokyo, Narita, pp.79-82.
  28. 楊博惠, 2009, Embedded All Digital Temperature Sensor, 2009 Conference on Innovative Applications of System Prototyping and Circuits Design, 2009/10/16, 清雲科技大學, 桃園,清雲科技大學. (嵌入式系統晶片之多點溫度感測電路設計研究)
  29. 楊博惠, 2009, All Digital Wide Rang Cyclic Sampling Pulsewidth Lock Loops, 2009 Conference on Innovative Applications of System Prototyping and Circuits Design, 2009/10/16, 清雲科技大學, 桃園,清雲科技大學. (嵌入式系統晶片之多點溫度感測電路設計研究)
  30. 楊博惠, 2009, A Recyclable Detection All Digital Pulsewidth Locked Loops, 2009 International Conference on High-Speed Circuit Design, 2009/10/04-07, 聖約翰科技大學, 台北縣,聖約翰科技大學. (嵌入式系統晶片之多點溫度感測電路設計研究)
  31. 楊博惠, 2009, A Low-Cost AND Operation Min-Sum Algorithm LDPC Decoder for IEEE 802.16e Application, 2009 VLSI Design / CAD Symposium, 2009/08/04-07, 國立中正大學, 花蓮. (MIMO傳送式之多畫面智慧型視訊安全監視系統研究)
  32. Po-Hui Yang; Jung-Chieh Chen; Ya-Ting Chan; Ming-Yu Lin, 2008, A Simplified Addition Operation Log-SPA LDPC Decoder, The 14th Asia-Pacific Conference on Communications, 2008/10/14-16, 東京.
  33. Po-Hui Yang; Ming-Jau shiau; Cheng-His Tsai, 2008, An All Digital Pulsewidth Locked Loops Using Recyclable Detection Technique, 2008 Asia-Pacific Chinese Conference on High-Speed Circiut Design (HSCD'08), 2008/07/22-23, 台北縣.
  34. Po-Hui Yang; Chun-Hung Lin; Kuen-Ru Tsai, 2008, An All Digital Embbed Multi-point Temperature Sensor System for SoC Applications, 2008 Asia-Pacific Chinese Conference on High-Speed Circiut Design (HSCD'08), 2008/07/22-23, 台北縣.
  35. Po-Hui Yang; Ming-Jau shiau; Cheng-His Tsai ; Jia-Shuo Liang, 2007, A Low- Power Embedded All Digital Temperature Sensor, 2007 Conference on Innovative Applications of System Prototyping and Circuit Design, 2007/09/28, 台南.
  36. Po-Hui Yang; Chun-Hung Lin; Kuen-Ru Tsai, 2007, Wide Frequency Range High-Speed All Digital Pulsewidth Locked Loops, 2007 Conference on Innovative Applications of System Prototyping and Circuit Design, 2007/09/28, 台南.
  37. 楊博惠, 2007, A low-Power Embedded All Digital Temperature Sensor, 2007 Conference on Innovative Applications of System Prototyping and Circuits Design, 2007/09/28, 台南市.
  38. 楊博惠, 2007, A New High-Speed Counter Based Viterbi Decoder, 2007 Conference on Innovative Applications of System Prototyping and Circuits Design, 2007/09/28, 台南市.
  39. 楊博惠, 2007, Wide Frequency Range High-Speed All Digital Pulsewidth Locked Loops, 2007 Conference on Innovative Applications of System Prototyping and Circuits Design, 2007/09/28, 台南市.
  40. 楊博惠, 2007, A Low-Complexity High-Performance Two-DimensionalLook-Up Table for LDPC Hardware Implementation, 2007 VLSI/CAD Symposium, 2007/08/07-10, 花蓮.
  41. 楊博惠, 2007, A Low-Hardware-Cost Logical OR Operation Log-SPA LDPC Decoder, 2007 VLSI/CAD Symposium, 2007/08/07-10, 花蓮.
  42. 楊博惠, 2006, 2006 Conference on Electronic Communication and Applications, A New High Speed Low Power Counter Based Viterbi Decoder, 2006/07/06, 高雄市, pp.175-178. (NSC95-2221-E-224-101)
  43. 賴義澤, 廖健棠, 楊博惠, 2006, 2006 Conference on Electronic Communication and Applications, A High-Bit Clear Normalization Technique for High-Speed and Low-Power Viterbi Decoder, 2006/07/06, 高雄市, pp.196-200. (NSC95-2221-E-224-101)
  44. Shuenn-Yuh Lee; Yueh-Lun Tsai; Wei-Zen Su; Po-Hui Yang, 2003, A 2.5 V switched-current sigma-delta modulator with a novel class AB memory cell.
  45. Po-Hui Yang, Jinn-Shyan Wang and Yi-Ming Wang, 2000, A 1-GHz low-power transposition memory using new pulse-clocked D flip-flops.
  46. Jinn-Shyan Wang; Po-Hui Yang, 2000, Power analysis and implementation of a low-power 300-MHz 8-b x 8-b pipelined multiplier.
  47. Jinn-Shyan Wang, Po-Hui Yang and Tseng, W., 1998, Low-power embedded SRAM macros with current-mode read/write operations.
  48. Jinn-Shyan Wang and Po-Hui Yang, 1998, A pulse-triggered TSPC flip-flop for high-speed low-power VLSI design applications.

三、技術報告

  1. 楊博惠, 2013, 無線通訊系統之低密度奇偶校驗碼低成本積體電路設計技術及其雛型系統建構. (執行期間:2008年05月01至2013年04月31日)

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國立雲林科技大學 電子工程系

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